Analog-to-digital converters are important components in digital signal processing. In this case, analog-to-digital converters convert the voltage of an input signal into a number proportional thereto, which is output as a digital signal. The digital signal is often a serial sequence of a number of bits, the binary value of the sequence representing the proportional number.
The number of bits per digital signal is a measure of its accuracy. An analog-to-digital converter having an accuracy of 8 bits converts an input signal into a binary sequence comprising 8 bits. The total input interval of an analog-to-digital converter is thus decomposed into a total of 256 partial intervals, a binary sequence of numbers comprising 8 bits being assigned to each partial interval beginning with the lowest. The lowest partial interval is assigned the decimal value 0 and the highest partial interval is assigned the decimal value 255.
The method of successive approximation is used in one possibility of realization for an analog-to-digital converter. Said method comprises a plurality of approximation steps, in each step a digital partial value being determined and used for forming the digital total value. In this case, the number of approximation steps corresponds to the binary accuracy of the digital value. A simple embodiment of such a method is described in detail in “Tietze/Schenk, Halbleiterschaltungstechnik [Semiconductor circuitry], 12th edition, Springer, 2002”, on page 1009 et seq.
In one variation of this method, an input signal or expediently the voltage of an input signal, in an approximation step, is not compared with one reference voltage or reference potential, but rather with two reference voltages or reference potentials. This involves determining whether the voltage of the input signal is greater or less than the two reference voltages or reference potentials or lies between the two. The two reference voltages or potentials thus subdivide the input interval for this approximation step into a total of three partial intervals, and the comparison determines that one of said three partial intervals in which the voltage of the input signal lies. Depending on the result, a new signal is generated and is used for the ensuing approximation step. Furthermore, each interval is assigned a value which is used for forming the digital output value of the analog-to-digital converter.
In practice, analog-to-digital converters with successive approximation operate in a clocked operating mode and are formed with sample-and-hold devices, each approximation step often being realized by circuits. During a sample phase, the input signals are sampled in the individual stages of the analog-to-digital converter. Signal processing is effected in a hold phase following the sample phase.
Rising clock rates lead to problems, however, in sample-and-hold circuits in the individual approximation stages of the analog-to-digital converter. In particular the sample-and-hold circuits which carry out a comparison of the input signal with the reference signals require time for their decision-making. At low clock rates, a short period of time between the sample phase and the hold phase is sufficient for decision-making, but at high clock rates the period of time is too short and the error rate rises greatly.
In order to prevent this, the comparison circuits of the individual approximation stages have been implemented such that they can make a decision as early as in a preceding time phase. As a result, the comparison circuits have a complete hold phase time for the decision. An analog-to-digital converter with such a “look-ahead technique” is shown in “Matsuura et. al, A 240-Mbps, 1-W CMOS EPRML Read-Channel LSI Chip Using an Interleaved Subranging Pipeline A/D Converter, IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, November 1998, page 1840 et seq.”. The major disadvantage of the analog-to-digital converter described therein, however, is its power consumption and its high supply voltage of 3.3 V, which is at odds with the requirement for a lower power consumption and small supply voltage. In addition, the problem of an excessively short period of time for decision-making is not solved completely in the case of this analog-to-digital converter.
A further analog-to-digital converter is described in U.S. Pat. No. 5,861,832. The last approximation stage of the converter therein is formed without additional amplifiers, whereby the current consumption and space taken up are reduced. However, the problem of an error-free conversion remains in this case, too.